FIG. 1 is a schematic circuit diagram illustrating a decoding circuit module for a memory according to the prior art. As shown in FIG. 1, the decoding circuit module comprises a high voltage (HV) decoding switch system 110 and a low voltage (LV) decoding switch system 150.
The HV decoding switch system 110 comprises a voltage switch circuit 120, a first voltage switch circuit module 130, and a decoding unit 140. According to a controlling signal EN, a first voltage HV or a second voltage MV is selectively outputted from the voltage switch circuit 120 to be used as an input voltage VPP of the decoding unit 140.
Moreover, the first voltage switch circuit module 130 comprises N voltage switch circuits. The configuration of each of the N voltage switch circuits of the first voltage switch circuit module 130 is similar to that of the voltage switch circuit 120. The first voltage switch circuit module 130 is controlled according to an N-bit address signal A<N−1:0>. Moreover, according to the N-bit address signal A<N−1:0>, an N-bit high voltage decoding signal HVDEC<N−1:0> is outputted from the first voltage switch circuit module 130 and inputted into the decoding unit 140.
For example, if the (N−1)-the bit address signal A[N−1] is at a low-level state (L), the (N−1)-the bit high voltage decoding signal HVDEC[N−1] is the first voltage HV. Whereas, if the (N−1)-th bit address signal A[N−1] is at a high-level state (H), the (N−1)-th bit high voltage decoding signal HVDEC[N−1] is the second voltage MV. The operations of other voltage switch circuits of the first voltage switch circuit module 130 are identical, and are not redundantly described herein.
After the input voltage VPP and the N-bit high voltage decoding signal HVDEC<N−1:0> are received by the decoding unit 140, different states (e.g. the on/off states) are generated in 2N array bus signal lines Array_bus<2N−1:0>. Since the decoding unit 140 is not the subject matter of the present invention, the circuitry and operating principles of the decoding unit 140 will not be illustrated herein.
Moreover, the LV decoding switch system 150 comprises a second voltage switch circuit module 160. The second voltage switch circuit module 160 comprises 2N voltage switch circuits. The output terminals of the 2N voltage switch circuits are connected to the 2N array bus signal lines Array_bus<2N−1:0>, respectively. The second voltage switch circuit module 160 is controlled according to the N-bit address signal A<N−1:0> and a read signal Read. The operations will be illustrated in more details as follows.
Take the (2N−1)-th array bus signal line Array_bus[2N−1] for example. In a case that the (2N−1)-th array bus signal line Array_bus[2N−1] is controlled by the decoding unit 140 to be turned on, the voltage at the (2N−1)-th array bus signal line Array_bus[2N−1] is the input voltage VPP. Meanwhile, the second voltage switch circuit module 160 is connected to the (2N−1)-th array bus signal line Array_bus[2N−1] in a floating state. Whereas, in a case that the (2N−1)-th array bus signal line Array_bus[2N−1] is controlled by the decoding unit to be turned off, the voltage at the (2N−1)-th array bus signal line Array_bus[2N−1] is provided by the second voltage switch circuit module 160. According to the N-bit address signal A<N−1:0> and a read signal Read, the second voltage switch circuit module 160 may provide 0V or a read voltage VR to the (2N−1)-th array bus signal line Array_bus[2N−1]. The operations of other array bus signal lines are similar, and are not redundantly described herein.
In a logic circuit manufacturing process, the voltage magnitude that is two times to three times the logic level voltage may be considered as a high voltage. For example, if the logic level voltage is 2.5V, the voltage higher than 7V may be considered as a high voltage. If the logic level voltage is 3.3V, the voltage higher than 9 may be considered as a high voltage. Whereas, if the logic level voltage is 5V, the voltage higher than 18V may be considered as a high voltage.
For example, in the decoding circuit module of the memory of FIG. 1, the logic level voltage is 5V, the first voltage HV is 18V, and the second voltage MV is 10V. That is, in the HV decoding switch system 110, the voltage switch circuit 120 and the first voltage switch circuit module 130 are both connected to the high voltage (i.e. the first voltage HV). Similarly, the high voltage (i.e. the first voltage HV) is received by the voltage switch circuits of the second voltage switch circuit module 160 in a specified situation.
Generally, a high voltage may be received by the logic circuit during operations. Since the high-voltage-receiving logic circuit is not compatible with the conventional logic circuit manufacturing process, the high-voltage-receiving logic circuit needs to be produced by a special logic circuit manufacturing process. Under this circumstance, the circuitry complexity of the logic circuit and the fabricating cost thereof are both increased. In other words, since the voltage switch circuit of FIG. 1 fails to be produced by the existing logic circuit manufacturing process, the voltage switch circuit needs to be produced by a special circuit manufacturing process and the fabricating cost is increased.
Therefore, there is a need of providing a voltage switch circuit which is produced by a logic circuit manufacturing process.